`timescale 1ns / 1ps

module mux41(
    input d0,input d1,input d2,input d3,
    input [1:0]s,
    output y0
    );

    reg temp;
    reg e0,e1,e2,e3;
    status_3 c1(d0,e0,temp);
    status_3 c2(d1,e1,temp);
    status_3 c3(d2,e2,temp);
    status_3 c4(d3,e3,temp);
    initial begin
        e0=0;e1=0;e2=0;e3=0;
        end
    always @(*) begin
        case(s)
            2'b00:e0=1;
            2'b01:e1=1;
            2'b10:e2=1;
            2'b11:e3=1;
            default:e0=1;
        endcase
        end
    assign y0=temp;
endmodule
